As well-known in the art, cell size within a semiconductor memory chip has become smaller as the chip is more highly integrated. Also, the operating voltage decreases due to meet requirements of the smaller-sized cell. Most semiconductor memory chips employ an operating voltage derived from an external power supply voltage VDD, but such a power supply voltage may introduce noise or change in its level. Therefore, an internal voltage generator has been provided within a chip to generate a stable internal voltage, in which a stable operation is always performed even in change of the external power supply voltage.
FIG. 1 is a block diagram of a conventional internal voltage generator.
Referring to FIG. 1, the internal voltage generator 20 for applying a core voltage VCORE to an internal circuit 10 includes a sense amplifier over driving portion 21, a core voltage supplier 22, a core voltage discharger 23 and a reference voltage generator 24.
Prior to describing the operation, various signals used therein are first defined as follows. An external voltage VR, which is a high voltage that may vary with a process, is divided to provide several reference voltages. A division control signal TRIM refers to a control signal to generate a constant supply reference voltage VREF based on the external voltage VR. The supply reference voltage VREF generally has ½ voltage level of required target value of the core voltage VCORE.
The circuit configurations of the sense amplifier over driving portion 21, the core voltage supplier 22 and the core voltage discharger 23 are already well-known in the art, and thus, details thereof will be omitted. The circuit configuration of the reference voltage generator 24 that is related to the present invention, however, will be illustrated below.
The following is a brief operation description of the sense amplifier over driving portion 21, the core voltage supplier 22 and the core voltage discharger 23.
The sense amplifier over driving portion 21 serves to apply a short circuit connection between an external power supply voltage VDD and the core voltage end VCORE and then apply the external power supply voltage VDD directly to the core voltage end VCORE so that sufficient core voltage VCORE is supplied to the internal circuit 10 when an activation signal Act (not shown) for activating the operation of Dynamic Random Access Memory (DRAM) is applied thereto.
The core voltage supplier 22 compares the supply reference voltage VREF with ½ voltage level of the core voltage VCORE (hereinafter, “half core voltage”) and charges the core voltage VCORE when the half core voltage is lower than the supply reference voltage VREF.
The core voltage discharger 23 compares the supply reference voltage VREF with the half core voltage and discharges the core voltage VCORE when the half core voltage is higher than the supply reference voltage VREF.
The reference voltage generator 24 divides the external voltage VR and provides a required voltage level among the divided external voltages as the supply reference voltage VREF in response to the division control signal TRIM.
FIG. 2 is a detailed circuit diagram of the reference voltage generator 24 shown in FIG. 1.
With reference to FIG. 2, the reference voltage generator 24 is provided with a voltage divider 27 for receiving and dividing an external voltage VR, and a reference voltage output portion 28 for providing one of voltage levels at nodes N1 to N3 of the voltage divider 27 as the supply reference voltage VREF depending on first to third division control signals TRIM1 to TRIM3.
To be more specific, the voltage divider 27 is composed of a plurality of resistors R1 to R4 connected in series between the external voltage end VR and a ground voltage end VSSA, and provides divided voltages into which the external voltage VR is divided at each of the nodes N1 to N3.
The reference voltage output portion 28 is composed of inverters INV1 to INV3 that receive the first to third division control signal TRIM1 to TRIM3, and first to third transfer gates G1 to G3 for outputting any one of the voltage levels at the first to third nodes N1 to N3 as the discharge reference voltage VREF in response to the first to third division control signal TRIM1 to TRIM3 and respective corresponding output signals of the inverters N1 to N3.
For example, if the voltage level at the second node N2 has the supply reference voltage VREF as required, the second division control signal TRIM2 becomes logic high and the first and third division control signals TRIM1 and TRIM3 become logic low. Thus, only the second transfer gate G2 is enabled and the divided external voltage level at the second node N2 is output as the supply reference voltage VREF.
Similarly, the voltage levels at the first node N1 and the third node N3 may be provided as the supply reference voltage VREF as required in response to the first to third division control signals TRIM1 to TRIM3.
FIG. 3 shows a simulation result for the input/output signals of the reference voltage generator 24 shown in FIG. 1. Here, the supply reference voltage VREF is one of the voltages into which the external voltage VR is divided and has a voltage level lower than that of the external voltage VR
FIG. 4 is a waveform for describing a change in voltage level of the core voltage VCORE created according to the prior art.
Referring to FIGS. 1 and 4, when an activation signal Act to activate the operation of DRAM is input, the core voltage VCORE is decreased by operation of the internal circuit 10 and the sense amplifier over driving portion 21 and the core voltage supplier 22 charges the decreased core voltage VCORE. In the meantime, the core voltage discharger 23 compares the supply reference voltage VREF with the half core voltage and discharges the core voltage VCORE if the half core voltage is higher than the supply reference voltage.
In other words, it can be seen that the internal voltage generator 20 according to the prior art provides the single supply reference voltage VREF generated by the reference voltage generator 24 to the core voltage supplier 22 and the core voltage discharger 23 as the reference voltage.
Accordingly, when the core voltage VCORE is discharged by the core voltage discharger 23, it is discharged beyond the target value of the core voltage VCORE due to a response speed delay of the core voltage discharger 23. The discharged core voltage VCORE is again charged by the core voltage supplier 22. For the above reason, the core voltage VCORE assumes an unstable, saw tooth like, waveform while repeating the charge and discharge operations.
The external voltage VR that may vary with a process is divided at each of the nodes N1 to N3 of the voltage divider 27 shown in FIG. 2 and a desired voltage level among the divided voltages can be provided as the supply reference voltage VREF as required according to the first to third division control signals TRIM1 to TRIM3.
However, since the core voltage supplier 22 and the core voltage discharger 23 receive the single constant supply reference VREF generated by the reference voltage generator 24, the core voltage VCORE has an unstable voltage level while repeating the charge and discharge operations owing to the response speed delay of the core voltage discharger 23.